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TPS23757
www.ti.com
SLVS948D – JULY 2009 – REVISED NOVEMBER 2013
? V ADPTR_ON - V PPDEN ÷ ? 18 V - 1.55 V ÷
R PPD1 = = ? ÷ = 31.64 k W
? V PPDEN ÷ ? ÷
+ 5 m A ÷
+ I PPD
? è 3.01 k W
? ÷ ?
è
(a)
? ? ? ?
? ÷
1.55 V
R PPD2 ?
(b) Choose R PPD1 = 32.4 k ?
5. Check PPD turn on and PPD turn off voltages
? V
? ( V PPDEN PPDH )
= ( V
) + ê R
? ÷ ú
ê ?
è ? ?
(a)
(b)
é ? ù
V ADPTR_ON = V PPDEN + ê R PPD1 ′ ? PPDEN + I PPD ÷ ú = 18.4 V
? ?
ê è R PPD2 ? ú
é - V ? ù
V ADPTR_OFF PPDEN - V PPDH PPD1 ′ ? + I PPD ÷ ú = 14.75 V
R PPD2
(c) Voltages look acceptable.
6. Check PPD resistor power consumption.
(V DD SS ) 2
( 24 V ′ 1.1 )
(a)
P RPPD
2
- V
= = = 19.6 mW
R PPD1 + R PPD2 3.01 k W + 32.4 k W
(b) Power is acceptable, but resistor values could be increased to reduce the power loss.
The PPD pin can also be used to modify the internal MOSFET UVLO for use with a lower output voltage PSE
(within certain limits). Connect the R PPD1 and R PPD2 dividers directly between VDD and VSS with the midpoint
connected to PPD. For this case and in order to allow classification, target the minimum PSE OFF voltage
(V ADPTR_OFF ) > V CU_OFF = 23V. Then follow the procedure outlined above to select R PPD1 , R PPD2 , and determine
the PSE ON (V ADPTR_ON ) and PSE OFF (V ADPTR_OFF ) voltages ensuring that PSE OFF > 23 V. Lastly, since the
R PPD1 / R PPD2 divider is in parallel with R DEN during detection, R DEN must be increased such that the equivalent
detection resistance is 25 k Ω nominal.
Setting Frequency (R FRS ) and Synchronization
The converter switching frequency is set by connecting R FRS from the FRS pin to ARTN. The frequency may be
set as high as 1 MHz with some loss in programming accuracy as well as converter efficiency. Synchronization
at high duty cycles may become more difficult above 500 kHz due to the internal oscillator delays reducing the
available on-time. As an example:
1. Assume a desired switching frequency (f SW ) of 250 kHz.
2. Compute R FRS :
(a)
17250 17250
R FRS (k W ) = = = 69
f SW (kHz) 250
(b) Select 69.8 k ? .
The TPS23757 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,
or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by
applying a short pulse (T SYNC ) of magnitude V SYNC to FRS as shown in Figure 25 . R FRS should be chosen so that
the maximum free-running frequency is just below the desired synchronization frequency. The synchronization
pulse terminates the potential on-time period, and the off-time period does not begin until the pulse terminates.
The pulse at the FRS pin should reach between 2.5 V and V B , with a minimum width of 22 ns (above 2.5 V) and
rise/fall times less than 10 ns. The FRS node should be protected from noise because it is high-impedance. An
R T on the order of 100 ? in the isolated example reduces noise sensitivity and jitter.
Copyright ? 2009–2013, Texas Instruments Incorporated
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